The present invention relates to a method of forming a flash memory cell using a hardmask and self-aligned source etch process.
As new technologies shrink the requirements put on the photolithographic process is becoming more stringent. This is especially the case in flash memory cell fabrication. Flash memory typically comprises a double polysilicon layer structure with a dielectric layer between the polysilicon layers. In fabricating this double polysilicon flash memory cell, photoresist is often used a mask during multiple etching process. This requirement places a limitation on the minimum thickness of photoresist that can be used. It is advantageous however to use a thin photoresist layer to improve the resolution of the lithography.
One of the etch process which the photoresist layer must withstand is the self-aligned source (SAS) etch process. In this process, regions of the silicon oxide isolation structures are removed to form a continuous conductive source line connecting numerous flash memory cells. The SAS etch usually comprises a plasma based silicon oxide etch. Because of limitations in forming a photoresist mask for the SAS etch process, a portion of the memory cell is usually exposed to the SAS etch. This often leads to removal of a portion of the upper polysilicon layer during the SAS etch process. There is therefore a need for a flash cell process in which thin photoresist is used while adequately protecting the memory cell during the SAS etch process.
The instant invention describes a method for forming a memory cell structure using a hardmask. The hardmask allows the utilization of thinner photoresist layers which improves the resolution of existing photoresist patterning techniques. In addition, the hardmask protects the polysilicon layer during the self-aligned source etch process. In particular the method comprises: providing a semiconductor substrate with isolation structures, a first dielectric layer, and a first polysilicon layer on said first dielectric layer; forming an inter-polysilicon dielectric layer on said first polysilicon layer; forming a second polysilicon layer on said inter-polysilicon layer; forming a hardmask layer on said second polysilicon layer; forming a patterned photoresist film on said hardmask layer; and etching said hardmask layer, said second polysilicon layer, and said inter-polysilicon dielectric layer with a multi-step etch process wherein said multi-step etch process removes said patterned photoresist layer.